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1. Acronyms

2. General

Compact, cost optimized, Traditional Split System and General Purpose L2/L3 IDU & Cell Site Gateway

IP-50GP will provide up to 4 radio interfaces to be used with any Ceragon BBI-connected RFUs, including RFU-D, RFU-D-HP, and the new RFU-S. IP-50GP will support configurations of up to 8 radio carriers, such as 8+0, 2x 4+0, and 4x 2+0, with efficient L1 aggregation.

IP-50GP will provide multiple 1/10/25GbE multi-rate ports, with very high switching capabilities, and will utilize radio-aware networking capabilities, such as SyncE, 1588v2-TC/BC, and Ethernet Bandwidth Notification (ETH-BN).

2.1. Product Overview

Traditional Split mount solution

• 1+0 /2+0 with RFU-D - replacing the retiring IP-20G/IP-20F/RFU-C

• Up to 8+0 with RFU-D /RFU-D-HP - cost optimized IP-20N use cases

Cost optimized L3 offering

• Cost optimized CSR and DAR router for price sensitive, non-TIP sensitive markets

• Business expectation, not including India, expected to be several thousands of units per year

NG Split mount solution

• vIDU with RAON and AODU - IP-50CX, IP-50EX, IP-100C-SM ( a low-cost option for the IP-50FX-200)

• Multiband solution – with IP-50EX + IP-50CX or RFU-D

• Business potential estimation is challenging, but it is on top of the other 2 use cases

There will be several flavors of the System -

• IDU – rackmount, L2 Switch CeraOS based with 2/4 BBIs

• IDU – rackmount, L2&L3 Switch OcNOS based or alike

• Outdoor aggregation unit - pole mount, fan-less (future)

2.1.1. IP-50GP – main features and components

• Common main board development for indoor and outdoor configuration

  • Split system

  • Digital to digital system

• Based on the Marvell® Prestera® 98DX35xx Series and Intel® Arria® 10 Device

The main functionality of the system is carried out using the Marvell switch.

In the eyes of the SW the FPGA ports acts as its remote ports.

The processor that is part of the switch constitutes the processor of the entire system.

Encryption enabled by utilizing MACsec encryption of the AC5X.

The FPGA performs additional functionality -

1. Application of deep buffers in favor of connecting radio heads and AODU systems that do not contain deep buffers.

2. Performing L1 aggregation using the CRB.
   Only the FPGA ports can support L1 aggregation using CRB.

3. Integrating the BBI to the system to enable connecting legacy RFUs to the system as traditional split system.

2.2. References and Standards

2.2.1. Networking

• MEF CE 2.0 compliance

• Ring/Mesh support – MSTP / G.8032

• Ethernet OAM Y.1731 FM

2.2.2. Synchronization

• Enhanced Ethernet Equipment Clock (eEEC) Specification (G.8262.1)

• PTP Telecom Boundary Clock (T-BC) and Time Slave Clock (T‑TSC) Spec (G.8273.2, Class C)

• PTP Telecom Transparent Clock (T-TC) Specification (G.8273.3, Class C)

• Enhanced SyncE Network Limits (G.8261, clause 9.2)

• Enhanced PTP Network Limits (G.8271.1)

• Ethernet Synchronization Messaging Channel (ESMC) (G.8264, clause 11)

• PTP Telecom Profile for Time (Full Timing Support) (G.8275.1)

• Precision Time Protocol (version 2, IEEE1588-2008)

2.2.3. Security

• MACsec 802.1AE

• FIPS 140-2

2.2.4. Safety

Compliance with the following standards is required:

• EN 62368-1

• IEC 62368-1

• UL 62368-1

• CAN/CSA-C22.2 No. 62368-1

2.2.5. EMC

The product shall meet EMC requirements in accordance with the following:

• EN 300 386 (class B)

• EN 301 489-4 (class B)

• EN 301 489-1 (class B)

• FCC 47 CFR, part 15, subpart B (class B)

• ICES-003 (class B)

• TEC/SD/DD/EMC-221/05/OCT-16

• EN 61000-4-5 level 3

• IEC 61000-4-29 – applicable only for direct DC, Criteria B

2.2.6. Transportation

The product shall meet requirements in accordance with the following:

• Classification: ETSI EN 300 019-1-2 Class 2.3

• Specification: ETSI EN 300 019-2-2 Specification T 2.3

2.2.7. Storage

The product shall meet requirements in accordance with the following:

• Classification: ETSI EN 300 019-1-1 Class 1.2

• Specification: ETSI EN 300 019-2-1 Specification T 1.2

2.2.8. Additional Requirements

The product shall comply with the following standards:

• RoHs – Restriction of Hazardous Substances according to Directive  2011/65/EU and its amendment 2015/863(EU).

• WEEE Compliance according to European Directive 2002/96/EC.

• REACH (EC 1907/2006)

3. Platform Overview

The IP-50GP product consists of following main components:

• Marvell AC5X switch, AC5X 98DX3510

  • Marvell AC5X switch internal CPU

  • Marvell AC5X CPU peripherals: eMMC, DDR4, Inventory Flash, and RTC 

• Intel® Arria® 10 Device, GX480 FPGA (the goal is to converge to 10AX048E2F29I2LG device)

  • DDR4 connected to it as buffers of the Traffic Managements modules in the FPGA.

• Marvell 88E6321 switch, serves as the management switch of the unit. 

  • OOB management and protection on unified RJ-45 connector.

• Switch networking interfaces: 2 x SFP28 25Gbps optical, 6 x 10Gbps SFP+ optical

• FPGA radio interfaces - 4 x SFP+ optical.

• -48V Power, single / dual feed input, power controller and secondary DC/DC

• On board JTAG connector

• Clock unit (system and SYNCE in same IC)

• USB 2.0 interface - mass storage. Assembly ready.

3.1. IP-50GP Indoor System Block Diagram 

4. Main Use-Cases

4.1. IP-50GP – Split system

4.1.1. Up-to 8+0

Traditional Split System up-to 8+0 using RFU-D/RFU-D-HP or 4+0 utilizing RFU-Sx

• Requires "deep buffers" (TM), CRB and 4 BBIs

• Each interface requires 2.5 Gbps for BBI connection to the RFU-D/RFU-D-HP/RFU-Sx

• Single direction

• CRB with 4 ports

• SBs for management, signaling and protocols

• RFU-S supported as well but provides less carriers in total

• Management of the RFU units done by the shelf comm. module via the MII interface through the management switch

Complies with PLM required use cases (single direction)–

• IP-50GP 1+0 with RFU-S /RFU-D Single Carrier

• IP-50GP 2+0 with RFU-D/RFU-D-HP Dual Carrier

• 2+0 with 2 RFU-S

• IP-50GP up to 8+0 with 4 x RFU-D/RFU-D-HP per site

• Internal Space Diversity using RFU-D/RFU-D-HP:

  • Up to 4+0 SD

• All configurations should support single or dual polarization (XPIC).

• 1+1 / 2+2 HSB SD 

4.1.2. Up-to 2x(4+0)

Traditional Split System up-to 2x(4+0) using RFU-Sx/RFU-D/RFU-D-HP

• Requires 2 TMs, 2 CRBs and 4 BBIs

• Each interface requires 2.5 Gbps for BBI connection to the RFU-D/RFU-D-HP

• East – West deployment

  • DSA tag support required

• SBs for management, signaling and protocols

• RFU-S supported as well but provides less carriers in total

• Management of the RFU units done by the shelf comm. module via the MII interface through the management switch

Complies with PLM required use cases (two directions) –

• IP-50GP 2x(1+0) –

  • 2x(1+0) with RFU-Sx /RFU-D Single Carrier

  • East – West deployment

• IP-50GP 2x(2+0) -

  • 2x(2+0) with 2 RFU-Sx /single RFU-D/ RFU-D-HP Dual carrier

  • East – West deployment

• IP-50GP 2x(4+0) –

  • IP-50GP 4+0 with 2x RFU-D per site

  • East – West deployment

• Internal Space Diversity

• XPIC support

4.1.3. Up-to 4 directions

Traditional Split System up-to 4x(2+0) RFU-D/RFU-D-HP

• Requires 4 TMs and 4 BBIs

• Each interface requires 2.5 Gbps for BBI connection to the RFU-D/RFU-D-HP

• 4 directions

  • East – west deployment

  • DSA tag support required

• SBs for management, signaling and protocols

• Complies with PLM required use cases –

  • IP-50GP Aggregation node use-case

• Management of the RFU units done by the shelf comm. module via the MII interface through the management switch

Complies with PLM required use cases (4 directions) –

• IP-50GP 4x(1+0) – RFU-S

• 4x(2+0) with RFU-D / RFU-D-HP, replacing IP-20N/A 1RU

4.2. IP-50GP Indoor system (deep buffers)

4.2.1. Up-to 4+0 E-band (IP-50EX with deep buffers)

Deep buffers for IP-50EX systems

• 4+0 configuration – single direction

  • 1 TM and 1 CRB (40Gbe) 

• 2x(2+0) configuration – two directions

  • 2 TMs and 2 CRBs

• 4x(1+0) – 4 directions

  • 4 TMs 

• Bypass the BBI - the 4 output interfaces from the FPGA can be configured either to 10G ethernet output or 2.5G BBI output

• DSA tag support in the switch and FPGA to support -

  • In-band management

  • Line protocols

  • 1588PTP

Complies with PLM required use cases –

• up to 4+0 with up to 4 IP-50EX

• up to 2x(2+0) with up to 4 IP-50EX

  • Two directions, East-West deployment

• up to 4x(1+0) with up to 4 IP-50EX

4.2.2. Multiband

4.2.2.1. IP-50EX + IP-50CX

Multiband configuration (IP50EX + IP50CX)

• Deep buffers for IP50EX/CX systems

  • Single direction

    • 1 TMs and 1 CRB

  • East – West deployment

    • 2 TMs and 2 CRBs

• Bypass the BBI - the 4 output interfaces from the FPGA can be configured either to 10G ethernet output or 2.5G BBI output

• DSA tag support in the switch and FPGA to support -

  • In-band management

  • Line protocols

  • 1588PTP

Complies with – IP-50GP Multi Band – IP-50CX & IP-50EX

4.2.2.2. Hybrid Connections – Ethernet and BBI (IP-50EX + RFU-S/D)

Multiband configuration (RFU-D + IP50EX) with deep buffers 

• Single direction

  • 1 TM and 1 CRB

• East – West deployment

  • 2 TM and 2 CRB

• Hybrid interfaces – BBI and Ethernet

• Management of the RFU units done by the shelf comm. module via the MII interface through the management switch

• DSA tag support in the switch and FPGA to support -

  • In-band management

  • Line protocols

  • 1588PTP

• Complies with PLM required use cases –

  • IP-50GP Multi Band - RFU-S & IP-50EX

  • IP-50GP Multi Band - RFU-D & IP-50EX (3 carriers)

4.3. Unit Protection

HW redundancy – no single point of failure

• OOB management and protection port

• Traffic connected by Y-cable

• Management and protection is connected through a WA-0720-0 splitter

  • The splitter cable constitutes of 2-pairs for 100M management via a splitter and a direct 100M connection between the units for protection. The splitter pinout is depicted in the diagram bellow -

Complies with – 1+1 (Radio & unit redundancy)

4.4. Indoor disaggregation use-cases

• Indoor system 

  • L2/L3 routing - future phase

  • Deep buffers for IP-50EX systems via the FPGA ports

• Up-to 198Gbps capacity switching

• AODU systems connections -

  • Ethernet user ports – connection directly to the Switch

  • FPGA ports – utilizing CRB to provide L1 aggregation and/or deep buffers

    • DSA tag support in the switch and FPGA to support -

      • In-band management

      • Line protocols

      • 1588PTP

• Multiple directions 

• User ports from the switch provide 25G interface toward IP-100E or other devices.

5. System HW Overview

System block diagram please see diagram 

5.1. IP-50GP - main interfaces (indoor - unit)

• 4x 1/2.5/10 Gbe or BBI ports (SFP+) - 2 of the interfaces are can be configured as User Ports

• 6x 1/10 GbE - user ports (SFP+)

• 2x 1/10/25 GbE ports - user ports (SFP28)

• 1x Management port (OOB management and protection port in single RJ-45)

• 1x Terminal port (RS232)

• 1x Sync port (1 PPS and ToD out)

• 1x USB 2.0 host-port - mass storage (Assembly ready)

• Single or dual DC feed

5.1.1. External Interfaces

If possible, it is required to examine the workability of the 4 ports that come out of the FPGA to also work as a single 40G port which consists of 4 lanes of 10G.

5.1.2. On-board connectors

5.2. IP-50GP Indoor Mechanics and Dimensions

The unit shall be indoor system mounted in a 19'' inch rack. It shall be 19'' and 1U height form factor.

• The unit weight shell not exceed 5.5KG.

• The system must be conduction cooled without fans, and according to the results of a thermal analysis.

5.3. IP-50GP Indoor System Power Dissipation Estimation

The table below contains rough estimates of power consumption for the main components of the system.

The total power consumption estimation of the full system configuration shell not exceed ~75W. 

5.4. 5.4. System front panel configuration

IP-50GP conceptual front panel configuration is depicted in the figure below -

(1) - Place holder for USB 2.0 port towards the AC5X, ready for L3 configuration

(2) - RJ-45 port, management and protection ports connected to the management SW

(3) - RJ-45 port, Terminal port (RS232). connected via RS232 buffer to the AC5X UART

(4) - RJ-45 port, Sync out. 1PPS and ToD out. From the AC5X via RS485 buffers.

(5) - 6 SFP+ ports towards the AC5X

(6) - 2 SFP28 ports towards the AC5X

(7) - 2 SFP+ ports towards the FPGA

(8) - DC, single or dual feed.

5.5. External Interfaces

5.5.1. P17, P18 - Power 

• The system shall be powered utilizing single or dual power feed

• Voltage Standard Input: -48 VDC; DC Input range: -40 to -60 VDC

• Support applicable power safety and EMC standards

• Power consumption ~75[W]

• Power connector as in former products

5.5.2. P1 - USB

• Connector type - USB 2.0 type A 

• Connected directly to AC5X 

• The USB to support mass storage, bootable DOK.

• The maximum current it provides to the USB client shell be limited to 0.5A.

5.5.3. P2 - Management / Protection

Out of band management and protection interfaces are connected to the same RJ-45 port - P2, the RJ45 port is connected directly to the PHY ports - P3 and P4 respectively of the management switch (Marvell 88E6320).

Protection interface is for management function between two units of IP-50GP, for example in the unit protection use-case.

• The port can be configured to the following speeds: 100M.

• Default rate is 100M, Auto-negotiation = ON, duplex = full duplex.

The wiring pin out of the combined port is depicted in the table below -

5.5.4. P3 - Terminal

• Connector type RJ45

• Connected directly to AC5X via RS232 buffer

The terminal connector pinout is defined by the table below.