Target release-platform | IP-50GP, CeraOS 13.1 |
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Epic | |
Document status | DRAFT |
Document owner | |
PLM | |
PM | |
HW Lead | |
FW Lead |
...
Table of content:
| Table of Contents | ||
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Table of figures:
List of tables
1. Acronyms
2. General
Compact, cost optimized, Traditional Split System and General Purpose L2/L3 IDU & Cell Site Gateway
IP-50GP will provide up to 4 radio interfaces to be used with any Ceragon BBI-connected RFUs, including RFU-D, RFU-D-HP, and the new RFU-S. IP-50GP will support configurations of up to 8 radio carriers, such as 8+0, 2x 4+0, and 4x 2+0, with efficient L1 aggregation.
IP-50GP will provide multiple 1/10/25GbE multi-rate ports, with very high switching capabilities, and will utilize radio-aware networking capabilities, such as SyncE, 1588v2-TC/BC, and Ethernet Bandwidth Notification (ETH-BN).
2.1. Product Overview
Traditional Split mount solution
1+0 /2+0 with RFU-D - replacing the retiring IP-20G/IP-20F/RFU-C
Up to 8+0 with RFU-D /RFU-D-HP - cost optimized IP-20N use cases
Cost optimized L3 offering
Cost optimized CSR and DAR router for price sensitive, non-TIP sensitive markets
Business expectation, not including India, expected to be several thousands of units per year
NG Split mount solution
vIDU with RAON and AODU - IP-50CX, IP-50EX, IP-100C-SM ( a low-cost option for the IP-50FX-200)
Multiband solution – with IP-50EX + IP-50CX or RFU-D
Business potential estimation is challenging, but it is on top of the other 2 use cases
There will be several flavors of the System -
IDU – rackmount, L2 Switch CeraOS based with 2/4 BBIs
IDU – rackmount, L2&L3 Switch OcNOS based or alike
Outdoor aggregation unit - pole mount, fan-less (future)
2.1.1. IP-50GP – main features and components
Common main board development for indoor and outdoor configuration
Split system
Digital to digital system
Based on the Marvell® Prestera® 98DX35xx Series and Intel® Arria® 10 Device
The main functionality of the system is carried out using the Marvell switch.
In the eyes of the SW the FPGA ports acts as its remote ports.
The processor that is part of the switch constitutes the processor of the entire system.
Encryption enabled by utilizing MACsec encryption of the AC5X.
The FPGA performs additional functionality -
Application of deep buffers in favor of connecting radio heads and AODU systems that do not contain deep buffers.
Performing L1 aggregation using the CRB.
Only the FPGA ports can support L1 aggregation using CRB.Integrating the BBI to the system to enable connecting legacy RFUs to the system as traditional split system.
2.2. References and Standards
2.2.1. Networking
MEF CE 2.0 compliance
Ring/Mesh support – MSTP / G.8032
Ethernet OAM Y.1731 FM
2.2.2. Synchronization
Enhanced Ethernet Equipment Clock (eEEC) Specification (G.8262.1)
PTP Telecom Boundary Clock (T-BC) and Time Slave Clock (T‑TSC) Spec (G.8273.2, Class C)
PTP Telecom Transparent Clock (T-TC) Specification (G.8273.3, Class C)
Enhanced SyncE Network Limits (G.8261, clause 9.2)
Enhanced PTP Network Limits (G.8271.1)
Ethernet Synchronization Messaging Channel (ESMC) (G.8264, clause 11)
PTP Telecom Profile for Time (Full Timing Support) (G.8275.1)
Precision Time Protocol (version 2, IEEE1588-2008)
2.2.3. Security
MACsec 802.1AE
FIPS 140-2
2.2.4. Safety
Compliance with the following standards is required:
EN 62368-1
IEC 62368-1
UL 62368-1
CAN/CSA-C22.2 No. 62368-1
2.2.5. EMC
The product shall meet EMC requirements in accordance with the following:
EN 300 386 (class B)
EN 301 489-4 (class B)
EN 301 489-1 (class B)
FCC 47 CFR, part 15, subpart B (class B)
ICES-003 (class B)
TEC/SD/DD/EMC-221/05/OCT-16
EN 61000-4-5 level 3
IEC 61000-4-29 – applicable only for direct DC, Criteria B
2.2.6. Transportation
The product shall meet requirements in accordance with the following:
Classification: ETSI EN 300 019-1-2 Class 2.3
Specification: ETSI EN 300 019-2-2 Specification T 2.3
2.2.7. Storage
The product shall meet requirements in accordance with the following:
Classification: ETSI EN 300 019-1-1 Class 1.2
Specification: ETSI EN 300 019-2-1 Specification T 1.2
2.2.8. Additional Requirements
The product shall comply with the following standards:
RoHs – Restriction of Hazardous Substances according to Directive 2011/65/EU and its amendment 2015/863(EU).
WEEE Compliance according to European Directive 2002/96/EC.
REACH (EC 1907/2006)
3. Platform Overview
The IP-50GP product consists of following main components:
Marvell AC5X switch, AC5X 98DX3510
Marvell AC5X switch internal CPU
Marvell AC5X CPU peripherals: eMMC, DDR4, Inventory Flash, and RTC
Intel® Arria® 10 Device, GX480 FPGA (the goal is to converge to 10AX048E2F29I2LG device)
DDR4 connected to it as buffers of the Traffic Managements modules in the FPGA.
Marvell 88E6321 switch, serves as the management switch of the unit.
OOB management and protection on unified RJ-45 connector.
Switch networking interfaces: 2 x SFP28 25Gbps optical, 6 x 10Gbps SFP+ optical
FPGA radio interfaces - 4 x SFP+ optical.
-48V Power, single / dual feed input, power controller and secondary DC/DC
On board JTAG connector
Clock unit (system and SYNCE in same IC)
USB 2.0 interface - mass storage. Assembly ready.
3.1. IP-50GP Indoor System Block Diagram
4. Main Use-Cases
4.1. IP-50GP – Split system
4.1.1. Up-to 8+0
Traditional Split System up-to 8+0 using RFU-D/RFU-D-HP or 4+0 utilizing RFU-Sx
Requires "deep buffers" (TM), CRB and 4 BBIs
Each interface requires 2.5 Gbps for BBI connection to the RFU-D/RFU-D-HP/RFU-Sx
Single direction
CRB with 4 ports
SBs for management, signaling and protocols
RFU-S supported as well but provides less carriers in total
Management of the RFU units done by the shelf comm. module via the MII interface through the management switch
Complies with PLM required use cases (single direction)–
IP-50GP 1+0 with RFU-S /RFU-D Single Carrier
IP-50GP 2+0 with RFU-D/RFU-D-HP Dual Carrier
2+0 with 2 RFU-S
IP-50GP up to 8+0 with 4 x RFU-D/RFU-D-HP per site
Internal Space Diversity using RFU-D/RFU-D-HP:
Up to 4+0 SD
All configurations should support single or dual polarization (XPIC).
1+1 / 2+2 HSB SD
4.1.2. Up-to 2x(4+0)
Traditional Split System up-to 2x(4+0) using RFU-Sx/RFU-D/RFU-D-HP
Requires 2 TMs, 2 CRBs and 4 BBIs
Each interface requires 2.5 Gbps for BBI connection to the RFU-D/RFU-D-HP
East – West deployment
DSA tag support required
SBs for management, signaling and protocols
RFU-S supported as well but provides less carriers in total
Management of the RFU units done by the shelf comm. module via the MII interface through the management switch
Complies with PLM required use cases (two directions) –
IP-50GP 2x(1+0) –
2x(1+0) with RFU-Sx /RFU-D Single Carrier
East – West deployment
IP-50GP 2x(2+0) -
2x(2+0) with 2 RFU-Sx /single RFU-D/ RFU-D-HP Dual carrier
East – West deployment
IP-50GP 2x(4+0) –
IP-50GP 4+0 with 2x RFU-D per site
East – West deployment
Internal Space Diversity
XPIC support
4.1.3. Up-to 4 directions
Traditional Split System up-to 4x(2+0) RFU-D/RFU-D-HP
Requires 4 TMs and 4 BBIs
Each interface requires 2.5 Gbps for BBI connection to the RFU-D/RFU-D-HP
4 directions
East – west deployment
DSA tag support required
SBs for management, signaling and protocols
Complies with PLM required use cases –
IP-50GP Aggregation node use-case
Management of the RFU units done by the shelf comm. module via the MII interface through the management switch
Complies with PLM required use cases (4 directions) –
IP-50GP 4x(1+0) – RFU-S
4x(2+0) with RFU-D / RFU-D-HP, replacing IP-20N/A 1RU
4.2. IP-50GP Indoor system (deep buffers)
4.2.1. Up-to 4+0 E-band (IP-50EX with deep buffers)
Deep buffers for IP-50EX systems
4+0 configuration – single direction
1 TM and 1 CRB (40Gbe)
2x(2+0) configuration – two directions
2 TMs and 2 CRBs
4x(1+0) – 4 directions
4 TMs
Bypass the BBI - the 4 output interfaces from the FPGA can be configured either to 10G ethernet output or 2.5G BBI output
DSA tag support in the switch and FPGA to support -
In-band management
Line protocols
1588PTP
Complies with PLM required use cases –
up to 4+0 with up to 4 IP-50EX
up to 2x(2+0) with up to 4 IP-50EX
Two directions, East-West deployment
up to 4x(1+0) with up to 4 IP-50EX
4.2.2. Multiband
4.2.2.1. IP-50EX + IP-50CX
Multiband configuration (IP50EX + IP50CX)
Deep buffers for IP50EX/CX systems
Single direction
1 TMs and 1 CRB
East – West deployment
2 TMs and 2 CRBs
Bypass the BBI - the 4 output interfaces from the FPGA can be configured either to 10G ethernet output or 2.5G BBI output
DSA tag support in the switch and FPGA to support -
In-band management
Line protocols
1588PTP
Complies with – IP-50GP Multi Band – IP-50CX & IP-50EX
4.2.2.2. Hybrid Connections – Ethernet and BBI (IP-50EX + RFU-S/D)
Multiband configuration (RFU-D + IP50EX) with deep buffers
Single direction
1 TM and 1 CRB
East – West deployment
2 TM and 2 CRB
Hybrid interfaces – BBI and Ethernet
Management of the RFU units done by the shelf comm. module via the MII interface through the management switch
DSA tag support in the switch and FPGA to support -
In-band management
Line protocols
1588PTP
Complies with PLM required use cases –
IP-50GP Multi Band - RFU-S & IP-50EX
IP-50GP Multi Band - RFU-D & IP-50EX (3 carriers)
4.3. Unit Protection
HW redundancy – no single point of failure
OOB management and protection port
Traffic connected by Y-cable
Management and protection is connected through a WA-0720-0 splitter
The splitter cable constitutes of 2-pairs for 100M management via a splitter and a direct 100M connection between the units for protection. The splitter pinout is depicted in the diagram bellow -
Complies with – 1+1 (Radio & unit redundancy)
4.4. Indoor disaggregation use-cases
Indoor system
L2/L3 routing - future phase
Deep buffers for IP-50EX systems via the FPGA ports
Up-to 198Gbps capacity switching
AODU systems connections -
Ethernet user ports – connection directly to the Switch
FPGA ports – utilizing CRB to provide L1 aggregation and/or deep buffers
DSA tag support in the switch and FPGA to support -
In-band management
Line protocols
1588PTP
Multiple directions
User ports from the switch provide 25G interface toward IP-100E or other devices.
5. System HW Overview
System block diagram please see diagram above.
5.1. IP-50GP - main interfaces (indoor - unit)
4x 1/2.5/10 Gbe or BBI ports (SFP+) - 2 of the interfaces are can be configured as User Ports
6x 1/10 GbE - user ports (SFP+)
2x 1/10/25 GbE ports - user ports (SFP28)
1x Management port (OOB management and protection port in single RJ-45)
1x Terminal port (RS232)
1x Sync port (1 PPS and ToD out)
1x USB 2.0 host-port - mass storage (Assembly ready)
Single or dual DC feed
5.1.1. External Interfaces
If possible, it is required to examine the workability of the 4 ports that come out of the FPGA to also work as a single 40G port which consists of 4 lanes of 10G.
5.1.2. On-board connectors
5.2. IP-50GP Indoor Mechanics and Dimensions
The unit shall be indoor system mounted in a 19'' inch rack. It shall be 19'' and 1U height form factor.
The unit weight shell not exceed 5.5KG.
The system must be conduction cooled without fans, and according to the results of a thermal analysis.
5.3. IP-50GP Indoor System Power Dissipation Estimation
The table below contains rough estimates of power consumption for the main components of the system.
The total power consumption estimation of the full system configuration shell not exceed ~75W.
| Note |
|---|
The final power consumption of each and every component in the system as well as the total consumption will be determined according to a detailed hardware design. |
5.4. 5.4. System front panel configuration
IP-50GP conceptual front panel configuration is depicted in the figure below -
(1) - Place holder for USB 2.0 port towards the AC5X, ready for L3 configuration
(2) - RJ-45 port, management and protection ports connected to the management SW
(3) - RJ-45 port, Terminal port (RS232). connected via RS232 buffer to the AC5X UART
(4) - RJ-45 port, Sync out. 1PPS and ToD out. From the AC5X via RS485 buffers.
(5) - 6 SFP+ ports towards the AC5X
(6) - 2 SFP28 ports towards the AC5X
(7) - 2 SFP+ ports towards the FPGA
(8) - DC, single or dual feed.
5.5. External Interfaces
5.5.1. P17, P18 - Power
The system shall be powered utilizing single or dual power feed
Voltage Standard Input: -48 VDC; DC Input range: -40 to -60 VDC
Support applicable power safety and EMC standards
Power consumption ~75[W]
Power connector as in former products
5.5.2. P1 - USB
Connector type - USB 2.0 type A
Connected directly to AC5X
The USB to support mass storage, bootable DOK.
The maximum current it provides to the USB client shell be limited to 0.5A.
5.5.3. P2 - Management / Protection
Out of band management and protection interfaces are connected to the same RJ-45 port - P2, the RJ45 port is connected directly to the PHY ports - P3 and P4 respectively of the management switch (Marvell 88E6320).
Protection interface is for management function between two units of IP-50GP, for example in the unit protection use-case.
The port can be configured to the following speeds: 100M.
Default rate is 100M, Auto-negotiation = ON, duplex = full duplex.
The wiring pin out of the combined port is depicted in the table below -
5.5.4. P3 - Terminal
Connector type RJ45
Connected directly to AC5X via RS232 buffer
The terminal connector pinout is defined by the table below.
5.5.5. P4 - Sync
Connector type RJ45
Connected directly to AC5X via RS485 buffers
The Sync connector pinout is defined by the table below.
5.5.6. P5, P6, P7, P8, P9, P10 - Ethernet
Connector type SFP+
All ports are connected directly to AC5X
Each port can be configured independently to the following speeds: 10G and 1G, as a function of SFP inserted to SFP+ cage.
Rate configuration shall be supported by CLI, REST and WEB.
Default rate is 10G, Auto-negotiation = OFF, duplex = full duplex.
5.5.7. P11, P12 - Ethernet
Connector type SFP28
Both ports are connected directly to AC5X
Each port can be configured independently to the following speeds: 25G, 10G and 1G, as a function of SFP inserted to SFP28 cage.
Rate configuration shall be supported by CLI, REST and WEB.
Default rate is 10G, Auto-negotiation = OFF, duplex = full duplex.
5.5.8. P13, P14, P15, P16 - Ethernet / BBI
Connector type SFP+
All ports are connected directly to the Arria 10 FPGA
Each port can be configured independently to the following speeds: 10G, 2.5G and 1G, as a function of its use Ethernet / BBI and the SFP inserted to SFP+ cage.
Rate configuration shall be supported by CLI, REST and WEB.Default rate in case of ethernet is 10G, Auto-negotiation = OFF, duplex = full duplex.
Default rate in case of BBI is 2.5G, Auto-negotiation = OFF, duplex = full duplex.
5.6. Interconnections
5.6.1. High speed interfaces
5.6.1.1. AC5X SerDes connections
See also
5.6.1.2. Management SW connections (Marvell 88E6321)
P0 of the management switch connected to the OOB of the AC5X directly.
P5 - MII interface between the management SW and the FPGA for control, configurations and statuses .
P3 - connected directly to to P1 of the system on the front panel
P4 - connected directly to to P2 of the system on the front panel
5.6.1.3. USB
Two USB interfaces are supported by AC5X CPU, one USB interface shall be used (USB0).
USB0 from AC5X CPU to USB port on the front panel. the interface to support mass storage devices as part of ONIE support for L3 solution.
5.6.2. Slow interfaces
5.6.2.1. SPI interfaces
5.6.2.1.1. 5.6.2.1.1. AC5X
The AC5X supports two SPI master interfaces:
Toward the FPGA for loading, configuration, and status. Use SPI of up to 50Mhz to make FPGA loading faster
Toward the inventory Serial Flash
TPM
As the AC5X has only two SPI busses, Inventory and TPM will share the same SPI
The AC5X shall control the MUX between the inventory and TPM using a GPIO, default is inventory.
5.6.2.1.2. FPGA
SPI Slave interfaces
SPI interface from the AC5X for FPGA loading and configuration.
5.6.2.2. I2C interfaces
5.6.2.2.1. AC5X
In the system architecture the AC5X supports one I2C master interfaces, the GPIOs of the second I2C that the AC5X have we be used in another purpose.
The I2C interface is connected to the following on board devices:
RTC
System Clk (CLU)
The devices have different I2C base addresses -
RTC -
In case of the DS1340 device the I2C base address will be - 1101000(R/W)
In case of the RV-3028 device the I2C base address will be - A5h/A4h (RD/WR) (1010010(R/W))
CLU
The I2C base address will be -10110A1A2 RD\RW (A1 and A2 are strip pins based on resisters)
The strip pins A0 and A1 are configured by CLU configuration software
5.6.2.2.2. FPGA
The FPGA shall support 13 I2C interfaces.
The I2C interfaces are connected to the following on board devices:
SFP28 → Ethernet - P5 (User port toward the AC5X)
SFP28 → Ethernet - P6 (User port toward the AC5X)
SFP+ → Ethernet - P7 (User port toward the AC5X)
SFP+ → Ethernet - P8 (User port toward the AC5X)
SFP+ → Ethernet - P9 (User port toward the AC5X)
SFP+ → Ethernet - P10 (User port toward the AC5X)
SFP+ → Ethernet - P11 (User port toward the AC5X)
SFP+ → Ethernet - P12 (User port toward the AC5X)
SFP+ → Ethernet - P13 (Port toward the FPGA)
SFP+ → Ethernet - P14 (Port toward the FPGA)
SFP+ → Ethernet - P15 (Port toward the FPGA)
SFP+ → Ethernet - P16 (Port toward the FPGA)
Power monitor - monitoring systems’ power (current, voltage, temperature)
5.6.2.3. MDIO
Management switch and management PHY are both connected to AC5X MDIO MPP[30,31]
Management switch MDIO address : 0X1F
Management PHY MDIO address : 0X0
5.6.2.4. RTC
Support RV-3028 RTC and DS1340 RTC
The design shall be similar to IP-100E and IP-50EX
5.6.2.5. UART
Two UARTs are supported by AC5X CPU:
UART1 from AC5X CPU to Terminal port on the front panel (RJ-45) via a RS232 buffer. In addition it shall be connected to a 6P header on the board (UART header, optional).
UART2 from AC5X CPU to Sync connector via RS485 buffer for ToD.
The UART header (6P header) pinout shall be as following:
5.6.3. GPIO
5.6.3.1. AC5X GPIO -
AC5X GPIOs are used also as special functions and configuration at reset, using internal and external PU/PDs
| Note |
|---|
Pull up and pull downs to MPP pins are important for MPP configuration at reset, the AC5X has default PU and PD, in case there is a change external PU or PD is required per table |
* Note: This pin functions as a “Sample at Reset” and thus should be pulled up/down per the required reset strapping value until reset is de-asserted. If used as a functional input (for GPIO or other), special care should be taken not to drive it differently during reset.
** Note: EMMC PHY has no internal default pulls (only the other MPP functionalities on these pins). All MMC pins must be PU on the board externally, except MMC_DS which should be PD externally
5.6.3.2. FPGA GPIO
TBD (FPGA HLF)
5.6.4. Memory Interfaces
5.6.4.1. eMMC
IP-50GP board must support a removable Ceragon eMMC card.
The eMMC is the disk for BOOT, software image and other mass storage applications
The supported size shall be at least 12GB (net storage). - In L2 configuration system. In order to support L3 configuration 32GB (net storage) shall be supported.
The eMMC shall be directly connected to Marvell AC5X switch. Two operational modes must be supported:
HS200 mode – up to 200 MHz, max data transfer of 200 MB/sec in 8-bit bus, 1.8V, applicable to bus width of 4/8 bits
HS400 Mode (including enhanced strobe mode) – up to 200 MHz, max data transfer of 400MB/sec in 8-bit bus, 1.8V, applicable to bus width of 8 bits
For support of HS400, an updated eMMC card is required - adding data-strobe (MMC_DS) signal, as it reduces BOOT time (Dual-Rate 400 MB/sec)
5.6.4.2. Secure BOOT
HW to support possibility to burn E-fuse - connect VHV pin to 1.8V in AC5X
5.6.4.3. TPM
Trusted Platform Module (TPM) provides a trusted zone for protected SW update and user data encryption
TPM isn't for AES-256 encryption
The TPM is used to save encryption keys with a secure access protocol.
The TPM should support revision 2.0
The access to the TMP is through SPI, connected directly to CPU
5.6.4.4. AC5X Boot Memory
AC5X BOOT is in the eMMC, does not require a serial flash
5.6.4.5. Inventory Serial Flash
Concept as in IP-50EX / IP-100E
Support 8Mb serial Flash, using SPI interface AC5X SPI for quick production access, instead of EEPROM, minimum data writes 10,000 cycles, 32Kbyte blocks
5.6.4.6. DDR
5.6.4.6.1. AC5X DDR
The DDR4 size required for L2 configuration supporting CeraOS + RAON is 4GB. The DDR size to support L3 Configuration is 8GB.
The design shall support maximum required DDR size as an assembly HW ready option. L2 system shall be assembled with 4GB DDRs
For the L2 configuration there shall be 2 chips of DDR4 of 2GB (DDR4 8bit 2400MT/s) with inline ECC shall be connected to the Marvell switch, AC5X.
using inline ECC will reduce BW and capacity by ~ 12%, not need for external DDR for ECC
Internal DDR for parity will be supported
5.6.4.6.2. FPGA DDR
64 bit @2400 MHz interface directly to the FPGA. (2133MHz rate shall be used due to FPGA speed grade)
Four DDR4 16 bit data each
At least 8Mbyte per queue, 8 queues per TM (up-to 4 TMs).
8 x 8 x 4 = 256M, the total size of the DDR4 to be connected to the FPGA shall be at least 256MB
6. Clocks and Synchronization
6.1. System Clock Tree
The system clock tree shall be depicted in
6.2. Synchronization
System synchronization diagram is depicted in .
The clock unit shall distribute ref_Clk to AC5X and FPGA
Recovered clock by the AC5X shall feed the CLU through mux in the FPGA as described in Recovery clock model
1PPS from CLU connection to the FPGA and AC5X is a backup option
6.2.1. CLU Connections
CLU support three PLLs:
A reference clock PLL for producing a clean REFCLK for CLU internal use, the REF PLL uses both the XO and TCXO
A system PLL for generating clean reference requirements of the clocks for ICs
A SyncE PLL to support SyncE standards
Inputs of recovery clock as described in section Recovery clock model
The outputs of reg_clk_25M are an alternative option to the connection of ref_clk that is shown in .
6.3. Marvel AC5X clock sources
The AC5X have two outputs of recovered clocks from SERDES ports, the frequency of ports is dependent on the SerDes configured rate, see , the applicable interface rates are SGMII (1G), 10G and 25G:
1g → 1
10G → 8
25G → 16
6.4. FPGA clock sources
The FPGA have 3 types of rates as sync source in the system -
2.5G - BBI → 25MHz
1G → 125MHz / 4 = 31.25Mhz
10G → 257.8125MHz / 8 = 32.2265625MHz
The 1G and 10G rates shall be similar to the recovery frequency of the AC5X.
The FPGA shall have an input of recovery clock from the Marvell and 4 outputs to the CLU.
6.5. Recovery clock model
Planning will be carried out to support 2 ways of changing the synchronization source in the system.
The first output of the recovered clock shall be connected directly to the CLU of the system.
The CLU configuration needs to be changed in case the SYNC source SERDES rate is changed. The configuration change should not require a CLU DPLL frequency change, also no reset should be done to CLU because of configuration change, as selected CLU supports input frequency change without reset.
CLU configuration shall be done by SW
No CLU configuration is required for system bring up process.
The CLU can be configured in automatic or manual mode, allowing the CLU to select between 4 inputs as SYNCE source with user assigned priority.
The second output of the recovered clock shall be connected to the FPGA.
The FPGA will do demultiplex of the input according to the rate of the clock and MUX with the internal recovered clock of the FPGA.
From the FPGA there shall be 4 outputs toward the CLU.
Changing the rate of the synchronization clock would be done selection of the corresponding input to the CLU without the need reconfigure the frequency.
6.6. SyncE and PTP support
The system shall support synchronization standards as listed in Synchronizations standards paragraph above.
6.6.1. IEEE-1588 support
For information only
IEEE-1588 BC and 1-step TC is supported by AC5X switch
The FPGA shall support 1-step TC
7. LEDs
7.1. Power Supply LEDs
One bi-color LED shall be placed under each power supply connector, the system have 2 power supply connectors.
The LED shall be Green when valid voltage is fed to the power connector
The LED shall be Red when invalid voltage is fed to the power connector
The LED shall be OFF when cable not connected
7.2. Management and protection Ports LEDs
Each of the management and protection ports will have one link/activity LED, these LEDs will be driven by management switch.
7.3. User Ports LEDs
User ports P5-P12 LEDs indications are outputted from AC5X through a serial channel and decoded in the FPGA, which drives the LEDs of the ports.
The serial channel is composed of LEDCLK, LEDSTB and LEDDATA.
The AC5X supports a frame structure that includes all LED indications per port. The required LED indications are link OK, and activity.
LED color – Green
Link OK – LED light
Activity – LED blink (per data rate nice to have)
The relevant ports for LED indications inside the AC5X are SERDESs 0-7.
7.3.1. AC5X LED controller configuration
As in IP-50EX and IP-100E
Single LED will be used as LED indication for link and activity, The controlled configuration as follows:
7.3.1.1. Link and Activity in Single LED Class
By using a single indication, the LED stream length is optimized according to the number of ports.
The most common use case is when the LED indicates both Link and Activity.
This section explains how to configure LED indication class 2 to reflect both Link and Activity in a
single indication. A single indication must reflect the status as follows:
Link Down – LED Off (assuming logical “0”)
Link Up – LED On (assuming logical “1”)
Rx/Tx Activity – LED Blinking (toggling 1/0)
This is achieved by:
Selecting the Activity indication
Causing the Activity indication to blink
Inverting the Activity indication
Disabling the Activity indication on link down
When there is no activity, the Activity indication is 0. Blinking has no affect. Inverting causes it to be 1. If the link is up, it stays 1. If the link is down, it is cleared to 0.
When there is an activity, the Activity indication is 1. Blinking causes it to toggle. Inverting has no meaning (due to toggling). Since the link is up, it is not disabled, thus keeps it in toggling state
(blinking).
All ports connected to the AC5X, shell be mapped to LED class 2
See section 60 of 98DX35xx functional data sheet for further details
7.4. FPGA Ports LEDs
In close proximity to each of the SFP+ connectors there is required to be a green LED.
Its functionality is determined by the configuration of the port.
7.4.1. Port Configured as BBI
The LED of the interface indicates the status of the IDU-RFU connection:
Off – The status of the radio unit is Disabled or cable is disconnected.
Green – A cable is connected between the interface and the RFU and communication between IDU and RFU has been established.
Slow Blinking Green – A cable is connected between the interface and the RFU, but communication has not been established between the IDU and the RFU.
This can be a temporary state while IDU-RFU communication is being established.Fast Blinking Green – There is an fault on the connection.
A cable is connected between the interface and the RFU and communication between the IDU and RFU has been established, but there is an alarm relating to the RFU.
7.4.2. Port Configured as Ethernet
The LED indicates the status of the Link:
Off – The interface is Disabled or cable is disconnected.
Green – A cable is connected to the interface and the Operational status of the link is Up.
Blinking Green – Activity - Traffic is passing on the interface
7.5. On-board indication LEDs
7.5.1. FPGA Status LED
FPGA status LED - conf_done LED.
The LED shall be green once the FPGA finished loading and the conf_done signal was raised.
7.5.2. Status LED
Status LED is an on-board bi-color LED, functionality according to the table below:
| Note |
|---|
The status LED light and blink controlled by Software |
8. DDM
DDM shall be supported as in former platforms
DDM shall be used for establishing the SFP information, temp , voltage … .
All SFP configuration and status shall be managed via FPGA I2C and GPIOs. Support Tx fault, Rx LOS and Tx mute.
9. Power - update
The system shall receive an external supply of -48V via one or two power interfaces (the second power interface is optional for power redundancy).
The 2 power inputs would be defined as the first one is primary and the other one is secondary. Meaning the primary power input would have priority over the secondary.
The system shall monitor the power supply for under-voltage and overvoltage.
The allowed power input range for the IP-50GP shall be -40V to -60V.
When input voltage is in the allowed range, power controller shall set green LED on that specific input. Otherwise, power controller shall set red LED.
The system would have an indication (notification for alarm) that the system switched from primary to secondary input power (the cause for switching can be either over voltage, under voltage or over current).
The notification won’t distinguish between the different causes.Once the cause for switching was cleared the system would switch back to primary power input.
An under-voltage alarm is triggered if the power goes below a defined threshold, and an overvoltage alarm is triggered if the power goes above a defined threshold.
The default thresholds are:
• Under-voltage Raise Threshold: 40V
• Under-voltage Clear Threshold: 42V
• Overvoltage Raise Threshold: 60V
• Overvoltage Clear Threshold: 58VThe thresholds for the under\over voltage shall be configurable.
The system shall include reverse polarity protection, so that if the positive (+) and negative (-) inputs are mixed up, the system remains shut down.
overvoltage and under-voltage alarms are raised specifically for the specific power input. A power input that is not in use can be masked in order to prevent unnecessary alarms.
System shall be able to hold at least 3msec at maximal power consumption after power input failure. On power failure, power controller shall send interrupt to FPGA.
10. Reset
Timing requirements for POR input to power outputs is 100mSec.
Timing requirements for POR input to reference clks and power inputs is at least 10mSec, 50mSec is required active with clocks active.
11. System BOOT
The system BOOT shall be done in parallel as possible to save system bring-up time, bring up time affects production time and cost.
The FPGA shall load from AC5X SPI
The AC5x shall BOOT from the eMMC.
11.1. FPGA configuration
MSEL configuration pins shall be set to PS at standard speed.
The FPGA configuration scheme shall be PS Device (Passive Serial)
The configuration and Initialization stages shall use the DCLK from the SPI, see
12. Environment Requirements
Temperature: -5°C (23°F) to 45°C (113°F) as per ETSI EN 300 019-2-3 Environmental class 3.2.
Humidity: 5%RH to 95%RHIngress protection) as per ETSI EN 300 019-2-3 & IEC 60529 IP20.
Temperature sensor in power supply, the CPU shall monitor the temperature. Temperature sensor shall give temperature reading for remote access.
When temperature rises above a given threshold, system's power shall be shutdown.
13. Debug capabilities
13.1. JTAG
The following JTAG targets shall be supported by one JTAG connector:
Marvel switch CPU has one JTAG for debug
FPGA connector for signal TAP
One Boundary Scan (BS) JTAG for production testing - default
External JTAG cable or card, AC5X debugger JTAG levels is 3.3V
In case debug of one of the above targets is required for debug than a jumper assembly change will be required to direct the JTAG connector to that target.
13.2. UART
Single on board UART connectors for AC5X CPU direct terminal access UART.
13.3. USB
The requirements shall be defined at L3 phase of the platform. Currently the USB is assembly ready only.
14. Testability
Support one JTAG connection for production boundary scan
One JTAG debug connection for AC5X
Support test points for analog and clock signals
For all the voltages in the circuit there will be test points in addition there will be indication LEDs on the card
FPGA indication LEDs like "conf_done"
14.1. Ethernet
Ethernet debug connection though management switch.
The connection to the AC5X will use the management connection
15. Production Support
BIST requirements shall be define in a dedicated HLF
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