...

• IDU – rackmount, L2 Switch CeraOS based with 2/4 BBIs

• IDU – rackmount, L2&L3 Switch OcNOS based or alike

• Outdoor aggregation unit - pole mount, fan-less (future)

2.1.1. IP-50GP – main features and components

• Common main board development for indoor and outdoor configuration

  • Split system

  • Digital to digital system

• Based on the Marvell® Prestera® 98DX35xx Series and Intel® Arria® 10 Device

...

• Marvell AC5X switch, AC5X 98DX3510

  • Marvell AC5X switch internal CPU

  • Marvell AC5X CPU peripherals: eMMC, DDR4, Inventory Flash, and RTC 

• Intel® Arria® 10 Device, GX480 FPGA (the goal is to converge to 10AX048E2F29I2LG device)

  • DDR4 connected to it as buffers of the Traffic Managements modules in the FPGA.

• Marvell 88E6321 switch, serves as the management switch of the unit. 

  • OOB management and protection on unified RJ-45 connector.

• Switch networking interfaces: 2 x SFP28 25Gbps optical, 6 x 10Gbps SFP+ optical

• FPGA radio interfaces - 4 x SFP+ optical.

• -48V Power, single / dual feed input, power controller and secondary DC/DC

• On board JTAG connector

• Clock unit (system and SYNCE in same IC)

• USB 2.0 interface - mass storage. Assembly ready.

...

• SPI interface from the AC5X for FPGA loading and configuration.

5.6.2.2. I²C interfaces

5.6.2.2.1. AC5X

In the system architecture the AC5X supports one I²C master interfaces, the GPIOs of the second I²C that the AC5X have we be used in another purpose.

The I²C interface is connected to the following on board devices:

...

The devices have different I²C base addresses -

• RTC - 

  • In case of the DS1340 device the I²C base address will be - 1101000(R/W)

  • In case of the RV-3028 device the I²C base address will be - A5h/A4h (RD/WR) (1010010(R/W))

• CLU 

  • The I²C base address will be -10110A1A2 RD\RW (A1 and A2 are strip pins based on resisters)

  • The strip pins A0 and A1 are configured by CLU configuration software

...

The FPGA shall support 13 I²C interfaces.

The I²C interfaces are connected to the following on board devices:

...

The AC5X have two outputs of recovered clocks from SERDES ports, the frequency of ports is dependent on the SerDes configured rate, see , the applicable interface rates are SGMII (1G), 10G and 25G:

1g → 1

10G → 8

25G → 16

6.4. FPGA clock sources

The FPGA have 3 types of rates as sync source in the system -

...

DDM shall be supported as in former platforms
DDM shall be used for establishing the SFP information, temp , voltage … .
All SFP configuration and status shall be managed via FPGA I2C and GPIOs. Support Tx fault, Rx LOS and Tx mute.

9. Power - update

• The system shall receive an external supply of -48V via one or two power interfaces (the second power interface is optional for power redundancy).

  • The 2 power inputs would be defined as the first one is primary and the other one is secondary. Meaning the primary power input would have priority over the secondary.

• The system shall monitor the power supply for under-voltage and overvoltage.

  • The allowed power input range for the IP-50GP shall be -40V to -60V.

    • When input voltage is in the allowed range, power controller shall set green LED on that specific input. Otherwise, power controller shall set red LED.

    • The system would have an indication (notification for alarm) that the system switched from primary to secondary input power (the cause for switching can be either over voltage, under voltage or over current).
      The notification won’t distinguish between the different causes.

    • Once the cause for switching was cleared the system would switch back to primary power input.

  • An under-voltage alarm is triggered if the power goes below a defined threshold, and an overvoltage alarm is triggered if the power goes above a defined threshold.

  • The default thresholds are:
    • Under-voltage Raise Threshold: 40V
    • Under-voltage Clear Threshold: 42V
    • Overvoltage Raise Threshold: 60V
    • Overvoltage Clear Threshold: 58V

  • The thresholds for the under\over voltage shall be configurable.

• The system shall include reverse polarity protection, so that if the positive (+) and negative (-) inputs are mixed up, the system remains shut down.

• overvoltage and under-voltage alarms are raised specifically for the specific power input. A power input that is not in use can be masked in order to prevent unnecessary alarms.

• System shall be able to hold at least 3msec at maximal power consumption after power input failure. On power failure, power controller shall send interrupt to FPGA.

...